The present invention relates to integrated circuit packaging, and more particularly, to inspection performed to detect die cracks in plastic encapsulated integrated circuits.
In general, a plastic encapsulated integrated circuit (PEIC) consists of a silicon chip, a metal support or leadframe, wires that electrically attach the chip circuits to the leadframe and thus to the external leads, and a plastic epoxy encapsulating material to protect the chip and the wire interconnects. The leadframe is made of a copper alloy, Alloy 42 (42Ni/58Fe) or Alloy 50 (50Ni/50Fe), and is plated with gold and silver or palladium, either completely or in selected areas over nickel or nickel/cobalt. The silicon chip is usually mounted to the leadframe with an organic conductive formulation of epoxy. Wires, generally of gold but also of aluminum or copper, are bonded to the aluminum bonding pads on the chips and to the fingers of the leadframe. The assembly is then typically transfer-molded in epoxy. Following the molding operations, the external pins are plated with a lead-tin alloy, cut away from the strip, and formed.
Plastic packages are either premolded or postmolded. In the former, a plastic base is molded, the chip is then placed on it and connected to an input/output fanout pattern with wire. The die and wirebonds are usually protected by an epoxy-attached lead, which forms a cavity. Premolded packages are most often used for high-pin-count devices or pin-grid arrays that are not amenable to flat leadframes and simple fanout patterns.
In the postmolded packages, the die is attached to a leadframe, which is then loaded into a multicavity molding tool and encapsulated in a thermoset molding compound via the transfer molding process. Postmolded packages are less expensive than premolded ones because are fewer parts and assembly steps. In the 1990s, about 90% of plastic packages were made using postmolding techniques. FIG. 1 illustrates various plastic package configurations having a die, an Alloy 42 or Cu leadframe, a heat fin and a heatsink.
Advantages of plastic packages over their ceramic counterparts include smaller form factors, lighter weight, better performance, and lower costs. The reliability of plastic packages has also increased substantially with improvements in encapsulants, die passivation, metallization technology, and assembly automation. However, during thermal processing, die scribing, dicing processes, or application of mechanical forces, die surface scratching and cracking may occur.
The location of a surface crack is critical, as a die surface crack across the device will cause electronic failures. Cracking can start as early as wafer fabrication. Lapping, which reduces sawing-introduced damage and thickness variations by obtaining a better degree of uniformity, induces crack growth. Also, stress imposed upon the crystal during cooling can cause cracking in the wafer. If no dislocation sources are present, the crystal will be highly stressed and can crack upon cooling.
A major cause of die cracking is the presence of voids. Cracks often occur at the corner of the die and initiate at an edge void. Also, rigid attachments cause the die to fracture during thermal cycling. FIG. 2 illustrates such types of die cracks as vertical cracks, horizontal cracks and slanting corner cracks.
In addition, plastic package cracks may form at delaminations at encapsulant interfaces with the die or the leadframe. The likelihood of the formation of plastic package cracks is directly proportional to the ratio of the die-paddle area to the minimum plastic case thickness. As illustrated in FIG. 3, plastic package cracks usually fall into one of three categories: I) the crack starts at the die paddle edge or comer and propagates to the bottom of the package; II) the crack starts at the die paddle edge or comer and propagates to the top of the package; III) the crack starts at the die edge or corner and propagates to the top of the package.
Current methods of crack inspection for plastic encapsulated integrated circuits require destructive techniques such as chemical decapsulation of the plastic package. Therefore, it would be desirable to create a non-destructive crack inspection technique to monitor assembly of plastic encapsulated integrated circuits. The non-destructive analysis would allow quicker crack inspection of large size samples. Also, non-destructive crack inspection would give information on the crack starting region and its propagation.
The present invention offers a novel method of non-destructive die crack inspection of a plastic encapsulated integrated circuit (PEIC). The method involves placing the PEIC in a sample chamber of a scanning acoustic microscope, such as a C-mode scanning acoustic microscope. To generate scan of a die surface of the PEIC, the width of a data gate of the microscope is set to scan only the die surface of the PEIC.
Further, the data gate may be moved to cover only die subsurface reflection area on a screen of the microscope, and scan of the die subsurface is generated.
In a preferred embodiment of the invention, the scan of the die surface is performed with the same resolution as the scan of the die subsurface.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.